diff --git a/src/RTLILParser/AST.hs b/src/RTLILParser/AST.hs
index f67731a..3ba776f 100644
--- a/src/RTLILParser/AST.hs
+++ b/src/RTLILParser/AST.hs
@@ -1,14 +1,43 @@
-module RTLILParser.AST(
-    AutoIdxStmt(..)    ,ParamStmt(..)       ,AutogenId(..)
-   ,Constant(..)       ,CellStmt(..)        ,PublicId(..)
-   ,AttrStmt(..)       ,Value(..)           ,Id(..)
-   ,CellId(..)         ,CellType(..)        ,WireId(..)
-   ,SigSpec(..)        ,Slice(..)           ,ConnStmt(..)
-   ,WireOption(..)     ,WireStmt(..)        ,Wire(..)
-   ,MemoryOption(..)   ,MemoryStmt(..)      ,Memory(..)
-   ,MemoryID(..)       ,CellBodyStmt(..)    ,ParameterSign(..)
-   ,Cell(..)
-    ) where
+module RTLILParser.AST (
+    -- Identifiers
+    Id(..), PublicId(..), AutogenId(..),
+
+    -- Values
+    Value(..),
+
+    -- Autoindex statements
+    AutoIdxStmt(..),
+
+    -- Module
+    ParamStmt(..), Constant(..),
+
+    -- Attribute statements
+    AttrStmt(..),
+
+    -- Signal Specifications
+    SigSpec(..), Slice(..),
+
+    -- Connections
+    ConnStmt(..),
+
+    -- Wires
+    Wire(..), WireStmt(..), WireId(..), WireOption(..),
+
+    -- Memories
+    Memory(..), MemoryStmt(..), MemoryID(..), MemoryOption(..),
+
+    -- Cells
+    Cell(..), CellStmt(..), CellId(..), CellType(..), ParameterSign(..),
+    CellBodyStmt(..),
+
+    -- Processes
+    DestSigSpec(..), SrcSigSpec(..), AssignStmt(..),
+
+    -- Switches
+    Switch(..), SwitchStmt(..), Case(..), CaseStmt(..), Compare(..),
+    CaseBodyVariants(..), CaseBody(..)
+) where
+
 import Text.Read (Lexeme(Ident))
 import Data.Functor.Contravariant (Contravariant)
 import GHC.RTS.Flags (DoCostCentres(CostCentresAll))
@@ -99,5 +128,23 @@ data CellBodyStmt   = CellBodyParameter
                     deriving (Show)
 
 -- Processes
+data DestSigSpec    = DestSigSpec SigSpec  deriving (Show)
+data SrcSigSpec     = SrcSigSpec  SigSpec  deriving (Show)
+data AssignStmt     = AssignStmt  DestSigSpec SrcSigSpec
+                    deriving (Show)
+
 -- Switches
+data Switch         = Switch SwitchStmt [AttrStmt] [Case]
+                      deriving (Show)
+data SwitchStmt     = SwitchStmt SigSpec [AttrStmt] deriving (Show)
+data Case           = Case CaseStmt [AttrStmt] [AssignStmt] CaseBody
+                      deriving (Show)
+data CaseStmt       = CaseStmt (Maybe Compare)
+                      deriving (Show)
+data Compare        = Compare SigSpec [SigSpec]
+                      deriving (Show)
+data CaseBodyVariants   = CaseBodySwitchVariant Switch
+                        | CaseBodyAssignVariant AssignStmt
+                        deriving (Show)
+data CaseBody       = CaseBody [CaseBodyVariants] deriving (Show)
 -- Syncs
\ No newline at end of file
diff --git a/src/RTLILParser/Parser.hs b/src/RTLILParser/Parser.hs
index b86abc3..599a1aa 100644
--- a/src/RTLILParser/Parser.hs
+++ b/src/RTLILParser/Parser.hs
@@ -3,18 +3,46 @@ module RTLILParser.Parser(a, val) where
 import Control.Monad (void)
 import Text.Parsec
 import Text.Parsec.String (Parser)
-import RTLILParser.AST(
-    AutoIdxStmt(..)    ,ParamStmt(..)       ,AutogenId(..)
-   ,Constant(..)       ,CellStmt(..)        ,PublicId(..)
-   ,AttrStmt(..)       ,Value(..)           ,Id(..)
-   ,CellId(..)         ,CellType(..)        ,WireId(..)
-   ,SigSpec(..)        ,Slice(..)           ,ConnStmt(..)
-   ,WireOption(..)     ,WireStmt(..)        ,Wire(..)
-   ,MemoryOption(..)   ,MemoryStmt(..)      ,Memory(..)
-   ,MemoryID(..)       ,CellBodyStmt(..)    ,ParameterSign(..)
-   ,Cell(..)
-    )
 import Util(binaryStringToInt)
+import RTLILParser.AST (
+    -- Identifiers
+    Id(..), PublicId(..), AutogenId(..),
+
+    -- Values
+    Value(..),
+
+    -- Autoindex statements
+    AutoIdxStmt(..),
+
+    -- Module
+    ParamStmt(..), Constant(..),
+
+    -- Attribute statements
+    AttrStmt(..),
+
+    -- Signal Specifications
+    SigSpec(..), Slice(..),
+
+    -- Connections
+    ConnStmt(..),
+
+    -- Wires
+    Wire(..), WireStmt(..), WireId(..), WireOption(..),
+
+    -- Memories
+    Memory(..), MemoryStmt(..), MemoryID(..), MemoryOption(..),
+
+    -- Cells
+    Cell(..), CellStmt(..), CellId(..), CellType(..), ParameterSign(..),
+    CellBodyStmt(..),
+
+    -- Processes
+    DestSigSpec(..), SrcSigSpec(..), AssignStmt(..),
+
+    -- Switches
+    Switch(..), SwitchStmt(..), Case(..), CaseStmt(..), Compare(..),
+    CaseBodyVariants(..), CaseBody(..)
+    )
 import RTLILParser.Primitives(
     pWs
    ,pNonWs
@@ -131,7 +159,7 @@ applySlices base = do
 pSlice :: Parser Slice
 pSlice =
     Slice
-    <$> (char '[' *> pMaybeWs *> pInteger <* pMaybeWs)
+    <$> (pMaybeWs *> char '[' *> pMaybeWs *> pInteger <* pMaybeWs)
     <*> (optionMaybe (char ':' *> pInteger) <* pMaybeWs <* char ']')
 
 -- Connections
@@ -233,10 +261,29 @@ pCellBodyConnect = do
     _       <- string "connect" <* pWs
     id      <- pId <* pWs
     sigSpec <- pSigSpec <* pEol
-    return $ CellConnect id sigSpec
+    return  $ CellConnect id sigSpec
 
 -- Processes
+pDestSigSpec :: Parser DestSigSpec
+pDestSigSpec = DestSigSpec <$> pSigSpec
+
+pSrcSigSpec :: Parser SrcSigSpec
+pSrcSigSpec = SrcSigSpec <$> pSigSpec
+
+pAssignStmt :: Parser AssignStmt
+pAssignStmt = AssignStmt
+    <$> (string "assign" *> pWs *> pDestSigSpec)
+    <*> (pWs *> pSrcSigSpec <* pEol)
+
 -- Switches
+pCaseStmt :: Parser CaseStmt
+pCaseStmt = CaseStmt
+    <$> (string "case" *> pWs *> optionMaybe pCompare <* pEol)
+
+pCompare :: Parser Compare
+pCompare = Compare
+    <$> pSigSpec
+    <*> many (char ',' *> pMaybeWs *> pSigSpec)
 -- Syncs