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This commit is contained in:
Yehowshua Immanuel 2023-09-25 03:34:21 -04:00
parent 1209f6a700
commit 257507e3fa
6 changed files with 108 additions and 2 deletions
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2
src/ClkDivider.bsv
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@ -21,7 +21,7 @@ module mkClkDivider#(Handle fileHandle)(ClkDivider#(hi));
hPutStr(fileHandle, genModuleName);
rule tick;
$display(counter);
// $display(counter);
counter <= (counter == hi_value) ? 0 : counter + 1;
endrule

53
src/Deserializer.bs
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@ -1,53 +0,0 @@
package Deserializer(
mkDeserialize,
IDeserializer(..),
State(..))
where
import ClkDivider
import State
interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
get :: Bit 8
putBitIn :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
mkDeserialize fileHandle = do
ftdiRxIn :: Wire(Bit 1) <- mkBypassWire
shiftReg :: Reg(Bit 8) <- mkReg(0)
ftdiState <- mkReg(IDLE)
clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
addRules $
rules
{-# ASSERT fire when enabled #-}
"IDLE" : when (ftdiState == IDLE), (ftdiRxIn == 0) ==>
do
clkDivider.reset
ftdiState := ftdiStateNext ftdiState
{-# ASSERT fire when enabled #-}
"NOT IDLE" : when (ftdiState /= IDLE), (clkDivider.isAdvancing) ==>
do
ftdiState := ftdiStateNext ftdiState
{-# ASSERT fire when enabled #-}
"SAMPLING" : when
DATA(n) <- ftdiState,
n >= 0,
n <= 7,
let sampleTrigger = clkDivider.isHalfCycle
in sampleTrigger
==>
do
shiftReg := ftdiRxIn ++ shiftReg[7:1]
return $
interface IDeserializer
{get = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
;putBitIn bit =
ftdiRxIn := bit
}

52
src/Deserializer.bsv Normal file
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@ -0,0 +1,52 @@
package Deserializer;
export mkDeserialize;
export IDeserializer(..);
export State(..);
import ClkDivider::*;
import State::*;
interface IDeserializer#(numeric type clkFreq, numeric type baudRate);
method Bit#(8) get();
method Action putBitIn(Bit#(1) bitIn);
endinterface
module mkDeserialize#(Handle fileHandle)(IDeserializer#(clkFreq, baudRate));
Wire#(Bit#(1)) ftdiRxIn <- mkBypassWire;
Reg#(Bit#(8)) shiftReg <- mkReg(0);
Reg#(State) ftdiState <- mkReg(IDLE);
ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
(* fire_when_enabled *)
rule idle (ftdiState == IDLE && ftdiRxIn == 0);
clkDivider.reset();
ftdiState <= ftdiStateNext(ftdiState);
endrule
(* fire_when_enabled *)
rule not_idle (ftdiState != IDLE && clkDivider.isAdvancing());
ftdiState <= ftdiStateNext(ftdiState);
endrule
(* fire_when_enabled *)
rule sampling (
ftdiState matches (tagged DATA .n) &&&
clkDivider.isHalfCycle()
);
shiftReg <= {ftdiRxIn, shiftReg[7:1]};
endrule
method Bit#(8) get() if (ftdiState == STOP && clkDivider.isAdvancing());
return shiftReg;
endmethod
method Action putBitIn(Bit#(1) bitIn);
ftdiRxIn <= bitIn;
endmethod
endmodule
endpackage

52
src/Serializer.bs
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@ -1,52 +0,0 @@
package Serializer(
mkSerialize,
ISerializer(..),
State(..))
where
import ClkDivider
import State
serialize :: State -> Bit 8 -> Bit 1
serialize ftdiState dataReg =
case ftdiState of
START -> 1'b0
(DATA n) -> dataReg[n:n]
_ -> 1'b1
interface (ISerializer :: # -> # -> *) clkFreq baudRate =
putBit8 :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
bitLineOut :: Bit 1 {-# always_ready #-}
mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
mkSerialize fileHandle = do
ftdiTxOut :: Wire(Bit 1) <- mkBypassWire
dataReg :: Reg(Bit 8) <- mkReg(0)
ftdiState <- mkReg(IDLE)
clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
addRules $
rules
{-# ASSERT fire when enabled #-}
"ADVANCE UART STATE WHEN NOT IDLE" : when
(ftdiState /= IDLE),
(clkDivider.isAdvancing) ==>
do
ftdiState := ftdiStateNext ftdiState
{-# ASSERT fire when enabled #-}
"BIT LINE" : when True ==>
do
ftdiTxOut := serialize ftdiState dataReg
return $
interface ISerializer
putBit8 bit8Val =
do
clkDivider.reset
dataReg := bit8Val
ftdiState := ftdiStateNext ftdiState
when (ftdiState == IDLE)
bitLineOut = ftdiTxOut

51
src/Serializer.bsv Normal file
View file

@ -0,0 +1,51 @@
package Serializer;
import ClkDivider::*;
import State::*;
export mkSerialize;
export ISerializer(..);
export State(..);
function Bit#(1) serialize(State state, Bit#(8) dataReg);
case (state) matches
tagged START : return 1'b0;
tagged DATA .n : return dataReg[n];
default : return 1'b1;
endcase
endfunction
interface ISerializer#(numeric type clkFreq, numeric type baudRate);
method Action putBit8(Bit#(8) bit8Val);
method Bit#(1) bitLineOut();
endinterface
module mkSerialize#(Handle fileHandle)(ISerializer#(clkFreq, baudRate));
Wire#(Bit#(1)) ftdiTxOut <- mkBypassWire();
Reg#(Bit#(8)) dataReg <- mkReg(0);
Reg#(State) ftdiState <- mkReg(IDLE);
ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
(* fire_when_enabled *)
rule advanceUartState (ftdiState != IDLE && clkDivider.isAdvancing());
ftdiState <= ftdiStateNext(ftdiState);
endrule
(* fire_when_enabled *)
rule bitLine (ftdiState != IDLE);
ftdiTxOut <= serialize(ftdiState, dataReg);
endrule
method Action putBit8(Bit#(8) bit8Val) if (ftdiState == IDLE);
clkDivider.reset();
dataReg <= bit8Val;
ftdiState <= ftdiStateNext(ftdiState);
endmethod
method Bit#(1) bitLineOut;
return ftdiTxOut;
endmethod
endmodule
endpackage