still workikng on Bus types

This commit is contained in:
Yehowshua Immanuel 2025-03-17 09:16:22 -04:00
parent 21a3ee7f7a
commit 550b3731b4
2 changed files with 85 additions and 3 deletions

View file

@ -6,6 +6,7 @@ import Serializer
import BRAM
import CBindings
import Bus
import List
type FCLK = 25000000
type BAUD = 9600
@ -16,19 +17,65 @@ interface ITop = {
;ftdi_txd :: Bit 1 -> Action {-# always_ready , always_enabled #-}
};
interface BusClient =
request :: Bit 1
response :: Bit 1 -> Action
mkBusClient :: Module BusClient
mkBusClient = module
reqReg :: Reg (Bit 1) <- mkReg 0
return $
interface BusClient
request = reqReg
response resp = do
reqReg := 0 -- Reset request after receiving response
interface Bus =
request :: Bit 1 -> Action
response :: Bit 1
mkBus :: Module Bus
mkBus = module
respReg :: Reg (Bit 1) <- mkReg 0
return $
interface Bus
request req = do
respReg := req -- Simple pass-through for this example
response = respReg
-- -- Function to connect Bus to BusClient
connectBusToClient :: Bus -> BusClient -> Rules
connectBusToClient bus client =
rules
"busConnection": when True ==> do
bus.request client.request
client.response bus.response
-- need to implement mkBus
-- need function that can connect Bus to BusClient
mkTop :: Module ITop
mkTop = do
fileHandle :: Handle <- openFile "compile.log" WriteMode
deserializer :: IDeserializer FCLK BAUD <- mkDeserialize fileHandle
serializer :: ISerializer FCLK BAUD <- mkSerialize fileHandle
core :: Core FCLK <- mkCore
bus :: Bus <- mkBus
busClient :: BusClient <- mkBusClient
let a :: List Integer = 1 :> 2 :> Nil
b = length a
persistLed :: Reg (Bit 8) <- mkReg 0
messageM $ "Hallo!!" + (realToString 5)
-- refactor such that the following rules are let-bound to
-- `attachIO` identifier
-- need to instantiate a Bus and BusClient
addRules $ connectBusToClient bus busClient
addRules $
rules
-- need new rule that always connects Bus to BusClient
"coreLedO" : when True ==>
persistLed := core.getLed