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scaffolding for new uart interface in place

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This commit is contained in:
Yehowshua Immanuel 2025-04-20 15:22:14 -04:00
parent 89664a01f6
commit 7290af88fb
4 changed files with 38 additions and 11 deletions
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8
bs/Uart/Deserializer.bs
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@ -1,6 +1,6 @@
package Deserializer(
mkDeserialize,
IDeserializer(..),
Deserializer(..),
State(..))
where
@ -8,11 +8,11 @@ import ClkDivider
import State
interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
interface (Deserializer :: # -> # -> *) clkFreq baudRate =
get :: Bit 8
putBitIn :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
mkDeserialize :: Handle -> Module (Deserializer clkFreq baudRate)
mkDeserialize fileHandle = do
ftdiRxIn :: Wire(Bit 1) <- mkBypassWire
shiftReg :: Reg(Bit 8) <- mkReg(0)
@ -46,7 +46,7 @@ mkDeserialize fileHandle = do
shiftReg := ftdiRxIn ++ shiftReg[7:1]
return $
interface IDeserializer
interface Deserializer
{get = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
;putBitIn bit =
ftdiRxIn := bit