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scaffolding for new uart interface in place

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This commit is contained in:
Yehowshua Immanuel 2025-04-20 15:22:14 -04:00
parent 89664a01f6
commit 7290af88fb
4 changed files with 38 additions and 11 deletions
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8
bs/Uart/Serializer.bs
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@ -1,6 +1,6 @@
package Serializer(
mkSerialize,
ISerializer(..),
Serializer(..),
State(..))
where
@ -14,11 +14,11 @@ serialize ftdiState dataReg =
(DATA n) -> dataReg[n:n]
_ -> 1'b1
interface (ISerializer :: # -> # -> *) clkFreq baudRate =
interface (Serializer :: # -> # -> *) clkFreq baudRate =
putBit8 :: (Bit 8) -> Action
bitLineOut :: Bit 1
mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
mkSerialize :: Handle -> Module (Serializer clkFreq baudRate)
mkSerialize fileHandle = do
ftdiTxOut :: Wire(Bit 1) <- mkBypassWire
@ -41,7 +41,7 @@ mkSerialize fileHandle = do
ftdiTxOut := serialize ftdiState dataReg
return $
interface ISerializer
interface Serializer
putBit8 bit8Val =
do
clkDivider.reset