scaffolding for new uart interface in place

This commit is contained in:
Yehowshua Immanuel 2025-04-20 15:22:14 -04:00
parent 89664a01f6
commit 7290af88fb
4 changed files with 38 additions and 11 deletions

26
bs/Uart/Uart.bs Normal file
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package Uart(
mkUartPhy,
UartPhy(..)
) where
import Serializer
import Deserializer
import BusTypes
import Util
-- Out is out from the FPGA and In is in to the FPGA
interface (UartPhy :: # -> # -> *) clkFreq baudRate =
bitOut :: Bit 1
bitIn :: Bit 1 -> Action
mkUartPhy :: (BusTypes.BusServer inFlightTransactions numClients)
-> Module (UartPhy clkFreq baudRate)
mkUartPhy dedicatedServerInterface = do
fileHandle :: Handle <- openFile "mkUartPhy.log" WriteMode
deserializer :: Deserializer clkFreq baudRate <- mkDeserialize fileHandle
serializer :: Serializer clkFreq baudRate <- mkSerialize fileHandle
return |>
interface UartPhy
bitOut = 1
bitIn bitVal = do
action {}