From e44f6b083b903493e886ef94b9b8edf8ce9b456f Mon Sep 17 00:00:00 2001
From: Yehowshua Immanuel <yehowshua@scaledintelligence.com>
Date: Wed, 20 Mar 2024 02:25:31 -0400
Subject: [PATCH] it's been a while

---
 .DS_Store                                     | Bin 0 -> 8196 bytes
 .gitignore                                    |  17 +++++++++++++++++
 Makefile                                      |   4 ++--
 README.md                                     |  18 ++++++++++++++++--
 experiments/.DS_Store                         | Bin 0 -> 6148 bytes
 experiments/bram/.DS_Store                    | Bin 0 -> 6148 bytes
 .../bram}/Testbench.bsv                       |   0
 {bram_tests => experiments/bram}/bram2.txt    |   0
 experiments/bram/sim_inspect.tcl              |  14 ++++++++++++++
 shell.nix                                     |  14 ++++++++++++++
 sim_inspect.tcl                               |  15 +++++++++++++++
 11 files changed, 78 insertions(+), 4 deletions(-)
 create mode 100644 .DS_Store
 create mode 100644 experiments/.DS_Store
 create mode 100644 experiments/bram/.DS_Store
 rename {bram_tests => experiments/bram}/Testbench.bsv (100%)
 rename {bram_tests => experiments/bram}/bram2.txt (100%)
 create mode 100644 experiments/bram/sim_inspect.tcl
 create mode 100644 shell.nix
 create mode 100644 sim_inspect.tcl

diff --git a/.DS_Store b/.DS_Store
new file mode 100644
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GIT binary patch
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diff --git a/.gitignore b/.gitignore
index fc6396a..8c3232b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,19 @@
 *.vcd
 *.so
+
+# bluespec files
+*.bo
+*.ba
+
+# files generated from building/simulating core
+compile.log
+build_v
+verilog_RTL
+
+# generated experiment outputs
+experiments/bram/*.cxx
+experiments/bram/*.h
+experiments/bram/simBRAM
+
+*.o
+.vscode
\ No newline at end of file
diff --git a/Makefile b/Makefile
index fedfcc1..a58066c 100644
--- a/Makefile
+++ b/Makefile
@@ -140,9 +140,9 @@ v_compile:
 	@echo Compiling for Verilog finished
 
 .PHONY: v_link
-v_link:
+v_link: $(BDPI_OBJ)
 	@echo Linking for Verilog sim ...
-	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v
+	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v 
 	@echo Linking for Verilog sim finished
 
 .PHONY: v_sim
diff --git a/README.md b/README.md
index 894d153..856b113 100644
--- a/README.md
+++ b/README.md
@@ -8,8 +8,18 @@ Just as "man does not live by bread alone, but by every word that proceeds from
 ``TOPMODULE=mkTop make v_compile`` to generate verilog. The generated verilog can
 be found in the ``verilog_RTL/`` folder.
 
+# Status
+Admittedly, not very far. Perhaps one could say we've got the beginnings 
+of what would make for LED and UART controllers.
+
 # Dependencies
-You'll need to install:
+## Linux
+Running `nix-shell` should *just work* on Linux. To be fair, haven't
+tested this yet.
+
+## MacOS
+Upstream nix recipes need to be adjusted a bit to work on MacOS, so
+for now do:
 1. [Yosys](https://github.com/YosysHQ/yosys) at git commit: 7ce5011c24b
 2. [nextpnr-0.4-36-gc8406b71](https://github.com/YosysHQ/nextpnr)
 3. [PrjTrellis](https://github.com/YosysHQ/prjtrellis) at git commit: 1.2.1-22-g35f5aff
@@ -26,16 +36,20 @@ screen /dev/tty.usbserial-K00027 9600
 ```
 
 # Simulation
+## Main Chip Core
 TODO
 
-# Generating Verilog
+## Experiments
+See experiments README.
 
+# Generating Verilog
 ```bash
 TOPMODULE=mkTop make v_compile
 ```
 
 # TODO
  - [ ] debug UART accuracy
+       - clk divider should be frequency matched
 
 # Notable Reference Files
 ``/Users/yehowshuaimmanuel/git/bsc/testsuite/bsc.bsv_examples/cpu/FiveStageCPUQ3sol.bsv``
\ No newline at end of file
diff --git a/experiments/.DS_Store b/experiments/.DS_Store
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diff --git a/experiments/bram/.DS_Store b/experiments/bram/.DS_Store
new file mode 100644
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diff --git a/bram_tests/Testbench.bsv b/experiments/bram/Testbench.bsv
similarity index 100%
rename from bram_tests/Testbench.bsv
rename to experiments/bram/Testbench.bsv
diff --git a/bram_tests/bram2.txt b/experiments/bram/bram2.txt
similarity index 100%
rename from bram_tests/bram2.txt
rename to experiments/bram/bram2.txt
diff --git a/experiments/bram/sim_inspect.tcl b/experiments/bram/sim_inspect.tcl
new file mode 100644
index 0000000..e691f96
--- /dev/null
+++ b/experiments/bram/sim_inspect.tcl
@@ -0,0 +1,14 @@
+# bluetcl sim_inspect.tcl
+namespace import ::Bluetcl::*
+package require Bluesim
+
+sim load simBRAM.so mkTestbench
+set count_hdl [sim lookup count]
+set bram [sim lookup dut1_memory]
+
+sim step
+sim step
+sim step
+
+puts "Value of count: [sim get $count_hdl]"
+puts "Value of bram\[0:3\]: [sim getrange $bram 0 3]"
diff --git a/shell.nix b/shell.nix
new file mode 100644
index 0000000..328453b
--- /dev/null
+++ b/shell.nix
@@ -0,0 +1,14 @@
+{ pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/d34a98666913267786d9ab4aa803a1fc75f81f4d.tar.gz") {} }:
+
+pkgs.mkShell {
+  buildInputs = [
+    pkgs.yosys
+    pkgs.nextpnr
+    pkgs.bluespec
+    pkgs.yosys-bluespec
+  ];
+
+  shellHook = ''
+    echo "Dev environment for Manna Chip."
+  '';
+}
\ No newline at end of file
diff --git a/sim_inspect.tcl b/sim_inspect.tcl
new file mode 100644
index 0000000..a4e560f
--- /dev/null
+++ b/sim_inspect.tcl
@@ -0,0 +1,15 @@
+# bluetcl sim_inspect.tcl
+namespace import ::Bluetcl::*
+package require Bluesim
+
+cd bram_tests
+sim load simBRAM.so mkTestbench
+set count_hdl [sim lookup count]
+set bram [sim lookup dut1_memory]
+
+sim step
+sim step
+sim step
+
+puts "Value of count: [sim get $count_hdl]"
+puts "Value of bram\[0:3\]: [sim getrange $bram 0 3]"
\ No newline at end of file