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ordered binary search working - but need to be sped up

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Yehowshua Immanuel 2022-08-06 21:40:33 -04:00
parent f1074e4340
commit b86e5fd3e4
3 changed files with 166 additions and 93 deletions
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146
src/vcd/types.rs
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@ -4,18 +4,27 @@ use chrono::prelude::*;
pub(super) struct Version(pub String);
#[derive(Debug)]
pub(super) enum Timescale {Fs, Ps, Ns, Us, Ms, S, Unit}
pub(super) enum Timescale {
Fs,
Ps,
Ns,
Us,
Ms,
S,
Unit,
}
#[derive(Debug)]
pub(super) struct Metadata {
pub(super) date : Option<DateTime<Utc>>,
pub(super) version : Option<Version>,
pub(super) timescale : (Option<u32>, Timescale)}
pub(super) date: Option<DateTime<Utc>>,
pub(super) version: Option<Version>,
pub(super) timescale: (Option<u32>, Timescale),
}
#[derive(Debug, Copy, Clone)]
pub(super) struct ScopeIdx(pub(super) usize);
#[derive(Debug, Copy, Clone)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub(super) struct SignalIdx(pub(super) usize);
#[derive(Debug, Copy, Clone)]
@ -25,63 +34,71 @@ pub(super) struct TimelineIdx(pub(super) u32);
pub struct StartIdx(pub(super) u32);
#[derive(Debug)]
pub(super) enum SigType {Integer, Parameter, Real, Reg, Str, Wire, Tri1, Time}
pub(super) enum SigType {
Integer,
Parameter,
Real,
Reg,
Str,
Wire,
Tri1,
Time,
}
#[derive(Debug)]
pub(super) enum Signal{
Data{
name : String,
sig_type : SigType,
// I've seen a 0 bit signal parameter in a xilinx
// simulation before that gets assigned 1 bit values.
// I consider this to be bad behavior. We capture such
// errors in the following type.
signal_error : Option<String>,
num_bits : Option<usize>,
// TODO : may be able to remove self_idx
self_idx : SignalIdx,
// we could encounter a mix of pure values and strings
// for the same signal timeline
u8_timeline : Vec<u8>,
u8_timeline_markers : Vec<TimelineIdx>,
string_timeline : Vec<String>,
string_timeline_markers : Vec<TimelineIdx>,
scope_parent : ScopeIdx},
Alias{
name : String,
signal_alias : SignalIdx}
pub(super) enum Signal {
Data {
name: String,
sig_type: SigType,
// I've seen a 0 bit signal parameter in a xilinx
// simulation before that gets assigned 1 bit values.
// I consider this to be bad behavior. We capture such
// errors in the following type.
signal_error: Option<String>,
num_bits: Option<usize>,
// TODO : may be able to remove self_idx
self_idx: SignalIdx,
// we could encounter a mix of pure values and strings
// for the same signal timeline
u8_timeline: Vec<u8>,
u8_timeline_markers: Vec<TimelineIdx>,
string_timeline: Vec<String>,
string_timeline_markers: Vec<TimelineIdx>,
scope_parent: ScopeIdx,
},
Alias {
name: String,
signal_alias: SignalIdx,
},
}
#[derive(Debug)]
pub(super) struct Scope {
pub(super) name : String,
pub(super) name: String,
pub(super) parent_idx : Option<ScopeIdx>,
pub(super) self_idx : ScopeIdx,
pub(super) child_signals : Vec<SignalIdx>,
pub(super) child_scopes : Vec<ScopeIdx>}
pub(super) parent_idx: Option<ScopeIdx>,
pub(super) self_idx: ScopeIdx,
pub(super) child_signals: Vec<SignalIdx>,
pub(super) child_scopes: Vec<ScopeIdx>,
}
// TODO: document how timeline is represented
#[derive(Debug)]
pub struct VCD {
pub(super) metadata : Metadata,
pub timeline : Vec<u8>,
pub timeline_markers : Vec<StartIdx>,
pub(super) all_signals : Vec<Signal>,
pub(super) all_scopes : Vec<Scope>,
pub(super) scope_roots : Vec<ScopeIdx>}
pub(super) metadata: Metadata,
pub timeline: Vec<u8>,
pub timeline_markers: Vec<StartIdx>,
pub(super) all_signals: Vec<Signal>,
pub(super) all_scopes: Vec<Scope>,
pub(super) scope_roots: Vec<ScopeIdx>,
}
impl VCD {
// TODO : make this a generic traversal function that applies specified
// TODO : make this a generic traversal function that applies specified
// functions upon encountering scopes and signals
fn print_scope_tree(
&self,
root_scope_idx : ScopeIdx,
depth : usize)
{
let all_scopes = &self.all_scopes;
fn print_scope_tree(&self, root_scope_idx: ScopeIdx, depth: usize) {
let all_scopes = &self.all_scopes;
let all_signals = &self.all_signals;
let indent = " ".repeat(depth * 4);
@ -94,17 +111,16 @@ impl VCD {
for SignalIdx(ref signal_idx) in &root_scope.child_signals {
let child_signal = &all_signals[*signal_idx];
let name = match child_signal {
Signal::Data{name, ..} => {name}
Signal::Alias{name, ..} => {name}
Signal::Data { name, .. } => name,
Signal::Alias { name, .. } => name,
};
println!("{indent} - sig: {name}")
}
println!();
for scope_idx in &root_scope.child_scopes {
self.print_scope_tree(*scope_idx, depth+1);
self.print_scope_tree(*scope_idx, depth + 1);
}
}
pub fn print_scopes(&self) {
@ -120,23 +136,23 @@ impl VCD {
for signal in &self.all_signals {
match signal {
Signal::Alias {..} => {}
Signal::Data {
name,
self_idx,
u8_timeline,
.. } => {
if u8_timeline.len() > max_len {
max_len = u8_timeline.len();
let SignalIdx(idx_usize) = self_idx;
idx = *idx_usize;
signal_name = name.clone();
}
Signal::Alias { .. } => {}
Signal::Data {
name,
self_idx,
u8_timeline,
..
} => {
if u8_timeline.len() > max_len {
max_len = u8_timeline.len();
let SignalIdx(idx_usize) = self_idx;
idx = *idx_usize;
signal_name = name.clone();
}
}
}
}
dbg!((idx, max_len, signal_name));
}
}
}