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Uart now has correct write implementation presumably

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Yehowshua Immanuel 2025-02-26 01:51:33 -05:00
parent 8d5cd862ab
commit 024115e389
6 changed files with 41 additions and 29 deletions
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14
hs/Bus.hs
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@ -4,6 +4,7 @@ module Bus() where
import Clash.Prelude
import Peripherals.Ram(Ram, RamLine, read, RamAddr)
import Peripherals.Uart(UartAddr, read)
import Machine(Peripherals(..))
import BusTypes(
BusError(..),
@ -35,10 +36,19 @@ alignCheck addr SizeQuadWord = addr `mod` 16 == 0
read :: Request -> Peripherals -> IO ReadResponse
read (Request addr size) peripherals
| not (alignCheck addr size) = return $ ReadResponse $ Error UnAligned
| (addr > ramStart) && (addr < ramEnd) =
return $ ReadResponse $ Result $ Peripherals.Ram.read size ramAddr (ram peripherals)
| (addr >= ramStart) && (addr <= ramEnd) =
return $
ReadResponse $
Result $ Peripherals.Ram.read size ramAddr (ram peripherals)
| (addr >= uartStart) && (addr <= uartEnd) =
ReadResponse . Result <$>
Peripherals.Uart.read size uartAddr
| otherwise = return $ ReadResponse $ Error UnMapped
where
ramAddrNoOffset = addr - ramStart
ramAddr :: RamAddr
ramAddr = resize ramAddrNoOffset
uartAddrNoOffset = addr - uartStart
uartAddr :: UartAddr
uartAddr = resize uartAddrNoOffset