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Replacing $ operator with more readable |> operator

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Yehowshua Immanuel 2025-03-06 08:41:00 -05:00
parent 2b1c486c17
commit 0792bf3c7d
12 changed files with 122 additions and 101 deletions
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21
hs/RegFiles.hs
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@ -22,6 +22,7 @@ module RegFiles(
) where
import Clash.Prelude
import Util((|>))
type GPR = Vec 32 (Unsigned 64) -- General Purpose Registers
type FPR = Vec 32 (Unsigned 64) -- Floating Point Registers
@ -64,16 +65,16 @@ csrNameToAddr MIMPID = 0xF13
-- are placeholders to be revisited for proper initialization later.
csrInit :: CSR
csrInit =
replace (csrNameToAddr STVEC) stvec_init
$ replace (csrNameToAddr SEPC) sepc_init
$ replace (csrNameToAddr MSTATUS) mstatus_init
$ replace (csrNameToAddr MISA) misa_init
$ replace (csrNameToAddr MTVEC) mtvec_init
$ replace (csrNameToAddr MEPC) mepc_init
$ replace (csrNameToAddr MVENDORID) mvendorid_init
$ replace (csrNameToAddr MARCHID) marchid_init
$ replace (csrNameToAddr MIMPID) mimpid_init
$ repeat 0
replace (csrNameToAddr STVEC) stvec_init |>
replace (csrNameToAddr SEPC) sepc_init |>
replace (csrNameToAddr MSTATUS) mstatus_init |>
replace (csrNameToAddr MISA) misa_init |>
replace (csrNameToAddr MTVEC) mtvec_init |>
replace (csrNameToAddr MEPC) mepc_init |>
replace (csrNameToAddr MVENDORID) mvendorid_init |>
replace (csrNameToAddr MARCHID) marchid_init |>
replace (csrNameToAddr MIMPID) mimpid_init |>
repeat 0
where
stvec_init = 0x0000000000002000 -- Supervisor mode trap vector base address.
sepc_init = 0x0000000000000000 -- Supervisor Exception PC initial value.