Yehowshua/RiscV-Formal
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Replacing $ operator with more readable |> operator

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Yehowshua Immanuel 2025-03-06 08:41:00 -05:00
parent 2b1c486c17
commit 0792bf3c7d
12 changed files with 122 additions and 101 deletions
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9
hs/Simulation.hs
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@ -21,6 +21,7 @@ import Cpu(
import Fetch(fetchInstruction, debugInsn)
import Decode(decode)
import qualified Prelude as P
import Util((|>))
data Args = Args {
firmware :: FilePath
@ -41,10 +42,10 @@ simulationLoop :: Int -> Machine -> IO [Machine]
simulationLoop 0 machine = return [machine]
simulationLoop n machine = do
let machinePeripherals = peripherals machine
currPc = pc $ cpu machine
currPc = pc |> cpu machine
fetchResult <- fetchInstruction machinePeripherals currPc
let decodeResult = decode fetchResult
putStrLn $ show decodeResult P.++ debugInsn fetchResult
putStrLn |> show decodeResult P.++ debugInsn fetchResult
let pc' = currPc + 4
cpu' = (cpu machine) { pc = pc' }
machine' = machine { cpu = cpu' }
@ -56,7 +57,7 @@ simulation :: Args -> IO Simulation
simulation args = do
initializedPeripherals <- setupPeripherals (firmware args)
case initializedPeripherals of
InitializationError e -> return $ Failure e
InitializationError e -> return |> Failure e
InitializedPeripherals ramDevice -> do
let initState =
@ -66,4 +67,4 @@ simulation args = do
}
sim <- simulationLoop 15 initState
teardownPeripherals
return $ Success sim
return |> Success sim