hopefully progressing to a more scalable bus architecture

hs/Bus.hs

@@ -0,0 +1,45 @@
+{-# OPTIONS_GHC -Wno-unrecognised-pragmas #-}
+module Bus() where
+
+import Clash.Prelude
+
+import Peripherals.Ram(Ram, RamLine)
+import Machine(Peripherals(..))
+import BusTypes(
+    BusError(..),
+    TransactionSize(..),
+    Request(..),
+    BusResponse(..),
+    BusVal(..),
+    ReadResponse(..),
+    WriteResponse(..)
+  )
+import Types(Addr,
+             Byte, HalfWord, FullWord, DoubleWord, QuadWord)
+
+alignCheck :: Addr -> TransactionSize -> Bool
+alignCheck addr SizeByte       = True
+alignCheck addr SizeHalfWord   = addr `mod` 2 == 0
+alignCheck addr SizeWord       = addr `mod` 4 == 0
+alignCheck addr SizeDoubleWord = addr `mod` 8 == 0
+alignCheck addr SizeQuadWord   = addr `mod` 16 == 0
+
+-- ram shoudl start at 0x80000000
+
+-- concatWords :: [Ram -> Addr -> RamLine] -> Ram -> Addr -> RamLine
+-- concatWords readers ram baseAddr = foldl (\acc f -> (acc `shiftL` 32) .|. f ram baseAddr) 0 readers
+
+-- read :: Request -> Peripherals -> ReadResponse
+-- read (Request addr size) peripherals
+--   | not (alignCheck addr size) = ReadError UnAligned
+--   | addr >= numBytesInRam      = ReadError UnMapped
+--   | otherwise                  =
+--     case size of
+--       SizeByte       -> BusByte $ fromIntegral $ extractByte (ramRead 0)
+--       SizeHalfWord   -> BusHalfWord $ fromIntegral $ (ramRead 0 `shiftL` 8) .|. ramRead 1
+--       SizeWord       -> BusWord $ fromIntegral $ concatReads [0..3]
+--       SizeDoubleWord -> BusDoubleWord $ fromIntegral $ concatReads [0..7]
+--       SizeQuadWord   -> BusQuadWord $ fromIntegral $ concatReads [0..15]
+--   where
+--     ramRead offset = Peripherals.Ram.read (ram peripherals) (fromIntegral (addr + offset))
+--     concatReads offsets = foldl (\acc o -> (acc `shiftL` 8) .|. ramRead o) 0 offsets