hopefully progressing to a more scalable bus architecture

hs/BusTypes.hs

@@ -0,0 +1,52 @@
+{-# OPTIONS_GHC -Wno-unrecognised-pragmas #-}
+module BusTypes(
+    BusError(..),
+    TransactionSize(..),
+    Request(..),
+    BusResponse(..),
+    BusVal(..),
+    ReadResponse(..),
+    WriteResponse(..)
+    ) where
+
+import Clash.Prelude
+
+import Peripherals.Ram(Ram, RamLine)
+import Machine(Peripherals(..))
+import Types(Addr,
+             Byte, HalfWord, FullWord, DoubleWord, QuadWord)
+
+data BusError
+    = UnMapped
+    | UnAligned
+    deriving (Generic, Show, Eq, NFDataX)
+
+data TransactionSize
+    = SizeByte
+    | SizeHalfWord
+    | SizeWord
+    | SizeDoubleWord
+    | SizeQuadWord
+    deriving (Generic, Show, Eq, NFDataX)
+
+data Request = Request Addr TransactionSize
+    deriving (Generic, Show, Eq, NFDataX)
+
+data BusResponse a
+    = Result a
+    | Error BusError
+    deriving (Generic, Show, Eq, NFDataX)
+
+data BusVal
+    = BusByte Byte
+    | BusHalfWord HalfWord
+    | BusWord FullWord
+    | BusDoubleWord DoubleWord
+    | BusQuadWord QuadWord
+    deriving (Generic, Show, Eq, NFDataX)
+
+newtype ReadResponse = ReadResponse (BusResponse BusVal)
+    deriving (Generic, Show, Eq, NFDataX)
+
+newtype WriteResponse = WriteResponse (BusResponse ())
+    deriving (Generic, Show, Eq, NFDataX)