hopefully progressing to a more scalable bus architecture

hs/Simulation.hs

@@ -48,10 +48,6 @@ machine' machine =
     peripherals' = machinePeripherals { ram = mem' }
     cpu' = machineCPU { pc = machinePC + 4 }
 
-    instruction =
-      case (fetchInstruction machineMem machinePC) of
-        Instruction i -> i
-        _ -> undefined
   in
     case (fetchInstruction machineMem machinePC) of
       Instruction insn ->
@@ -68,6 +64,9 @@ simulationLoop :: Int -> Machine -> IO [Machine]
 simulationLoop 0 state = return [state]
 simulationLoop n state = do
   let newState = machine' state
+  -- later use this to display writes from machine to its
+  -- uart peripheral
+  -- writeCharToTerminal 'a'
   rest <- simulationLoop (n - 1) newState
   return (state : rest)