hopefully progressing to a more scalable bus architecture
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13 changed files with 187 additions and 46 deletions
12
hs/Types.hs
12
hs/Types.hs
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@ -1,7 +1,9 @@
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Types(Pc, BusVal(..), Mem, FullWord, Insn, Addr) where
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module Types(Pc, Mem, Insn, Addr,
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Byte, HalfWord, FullWord, DoubleWord, QuadWord)
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where
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import Clash.Prelude
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@ -12,14 +14,6 @@ type DoubleWord = Unsigned 64
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type QuadWord = Unsigned 128
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type Insn = FullWord
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data BusVal
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= BusByte Byte
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| BusHalfWord HalfWord
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| BusWord FullWord
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| BusDoubleWord DoubleWord
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| BusQuadWord QuadWord
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deriving (Generic, Show, Eq, NFDataX)
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type Pc = DoubleWord
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type Addr = DoubleWord
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type Mem n = Vec n FullWord
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