hopefully progressing to a more scalable bus architecture

This commit is contained in:
Yehowshua Immanuel 2025-02-25 14:24:54 -05:00
parent 003a1c8545
commit 1f9bd2f015
13 changed files with 187 additions and 46 deletions

View file

@ -1,7 +1,9 @@
{-# LANGUAGE DataKinds #-}
{-# LANGUAGE NumericUnderscores #-}
module Types(Pc, BusVal(..), Mem, FullWord, Insn, Addr) where
module Types(Pc, Mem, Insn, Addr,
Byte, HalfWord, FullWord, DoubleWord, QuadWord)
where
import Clash.Prelude
@ -12,14 +14,6 @@ type DoubleWord = Unsigned 64
type QuadWord = Unsigned 128
type Insn = FullWord
data BusVal
= BusByte Byte
| BusHalfWord HalfWord
| BusWord FullWord
| BusDoubleWord DoubleWord
| BusQuadWord QuadWord
deriving (Generic, Show, Eq, NFDataX)
type Pc = DoubleWord
type Addr = DoubleWord
type Mem n = Vec n FullWord