created Decode result

hs/Fetch.hs

@@ -3,10 +3,12 @@
 
 module Fetch(
   fetchInstruction,
+  debugInsn,
   FetchResult(..),
   ) where
 
 import Clash.Prelude
+import qualified Prelude as P
 import Types(Addr, Insn)
 import Bus(read)
 import Bus(Peripherals(..))
@@ -19,6 +21,7 @@ import Exceptions(Exception(..))
 
 data FetchResult  = Instruction Insn
                    | InstructionException Exception
+                   deriving (Generic, Show, Eq, NFDataX)
 
 fetchInstruction :: Peripherals -> Addr -> IO FetchResult
 fetchInstruction peripherals addr =
@@ -28,8 +31,19 @@ fetchInstruction peripherals addr =
       Right (BusFullWord insn) ->
         pure $ Instruction insn
       Left  UnAligned ->
-        pure $ InstructionException InstructionAddressMisaligned
+        pure $ InstructionException (InstructionAddressMisaligned addr)
       Left  UnMapped ->
-        pure $ InstructionException InstructionAccessFault
+        pure $ InstructionException (InstructionAccessFault addr)
       Right _ ->
-        pure $ InstructionException InstructionAccessFault
+        pure $ InstructionException (InstructionAccessFault addr)
+
+debugInsn :: FetchResult -> String
+debugInsn fetchResult = 
+  case fetchResult of
+    Instruction insn ->
+      "Instruction raw binary | " 
+        P.++ binaryInsn
+        P.++ " (" P.++ show insn P.++ ")"
+      where
+        binaryInsn = show (bitCoerce insn :: BitVector 32)
+    InstructionException e -> show e