created Decode result

hs/Simulation.hs

@@ -11,7 +11,6 @@ module Simulation(
   Simulation(..)
   ) where
 
-import qualified Prelude as P
 import Peripherals.Setup(setupPeripherals, InitializedPeripherals(..))
 import Peripherals.Teardown(teardownPeripherals)
 import Clash.Prelude
@@ -19,8 +18,9 @@ import Bus(Peripherals(..))
 import Cpu(
   RISCVCPU(..),
   riscvCPUInit)
-import Fetch(fetchInstruction, FetchResult (..))
+import Fetch(fetchInstruction, debugInsn)
 import Decode(decode)
+import qualified Prelude as P
 
 data Args = Args {
     firmware :: FilePath
@@ -36,17 +36,6 @@ data Machine = Machine
   }
   deriving (Generic, Show, Eq, NFDataX)
 
-debugInsn :: FetchResult -> String
-debugInsn fetchResult = 
-  case fetchResult of
-    Instruction insn ->
-      "Decoded instruction: " P.++ show opcode
-                      P.++ " | Binary: " P.++ binaryInsn
-                      P.++ " (" P.++ show insn P.++ ")"
-      where
-        binaryInsn = show (bitCoerce insn :: BitVector 32)
-        opcode = decode insn
-    InstructionException e -> show e
 
 simulationLoop :: Int -> Machine -> IO [Machine]
 simulationLoop 0 machine = return [machine]
@@ -54,7 +43,8 @@ simulationLoop n machine = do
   let machinePeripherals = peripherals machine
       currPc = pc $ cpu machine
   fetchResult <- fetchInstruction machinePeripherals currPc
-  putStrLn $ debugInsn fetchResult
+  let decodeResult = decode fetchResult
+  putStrLn $ show decodeResult P.++ debugInsn fetchResult
   let pc' = currPc + 4
       cpu' = (cpu machine) { pc = pc' }
       machine' = machine { cpu = cpu' }