replace/update relevant fetch types and functions
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2 changed files with 8 additions and 48 deletions
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@ -19,7 +19,7 @@ import Bus(Peripherals(..))
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import Cpu(
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RISCVCPU(..),
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riscvCPUInit)
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import Fetch(fetchInstruction, FetchResult (Instruction, Misaligned), fetchInstruction1, FetchResult1(..))
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import Fetch(fetchInstruction, FetchResult (..))
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import Isa.Decode(decode)
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import Debug.Trace
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@ -40,31 +40,10 @@ data Machine = Machine
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}
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deriving (Generic, Show, Eq, NFDataX)
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machine' :: Machine -> Machine
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machine' machine =
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let
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machinePeripherals = peripherals machine
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machineMem = ram $ machinePeripherals
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machineCPU = cpu machine
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machinePC = pc machineCPU
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cpu' = machineCPU { pc = machinePC + 4 }
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in
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case (fetchInstruction machineMem machinePC) of
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Instruction insn ->
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let binaryInsn = show (bitCoerce insn :: BitVector 32)
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in trace ("Decoded instruction: " P.++ show opcode
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P.++ " | Binary: " P.++ binaryInsn
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P.++ " (" P.++ show insn P.++ ")") $
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machine { cpu = cpu' }
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where
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opcode = decode insn
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Misaligned addr -> undefined
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debugInsn :: FetchResult1 -> String
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debugInsn :: FetchResult -> String
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debugInsn fetchResult =
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case fetchResult of
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Instruction1 insn ->
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Instruction insn ->
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"Decoded instruction: " P.++ show opcode
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P.++ " | Binary: " P.++ binaryInsn
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P.++ " (" P.++ show insn P.++ ")"
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@ -76,15 +55,13 @@ debugInsn fetchResult =
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simulationLoop :: Int -> Machine -> IO [Machine]
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simulationLoop 0 machine = return [machine]
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simulationLoop n machine = do
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-- let newState = machine' machine
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let machinePeripherals = peripherals machine
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currPc = pc $ cpu machine
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fetchResult <- fetchInstruction1 machinePeripherals currPc
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fetchResult <- fetchInstruction machinePeripherals currPc
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putStrLn $ debugInsn fetchResult
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let pc' = currPc + 4
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cpu' = (cpu machine) { pc = pc' }
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machine' = machine { cpu = cpu' }
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-- let machine' = machine { cpu = cpu $ machine { pc = pc $ cpu machine + 4 } }
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rest <- simulationLoop (n - 1) machine'
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return (machine : rest)
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