Yehowshua/RiscV-Formal
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added basic decoding

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Yehowshua Immanuel 2025-02-19 01:21:02 -05:00
parent ef58d5b07e
commit 32932f4816
7 changed files with 289 additions and 61 deletions
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3
hs/Simulation.hs
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@ -47,9 +47,6 @@ machine' machine =
in
machine { cpu = cpu', mem = mem' }
machineSignal :: HiddenClockResetEnable dom => Signal dom Machine
machineSignal = register machine (machine' <$> machineSignal)
simulationLoop :: Int -> Machine -> IO [Machine]
simulationLoop 0 state = return [state]
simulationLoop n state = do