bus architecture re-built I think

hs/Bus.hs

@@ -1,25 +1,45 @@
 {-# OPTIONS_GHC -Wno-unrecognised-pragmas #-}
-module Bus() where
+module Bus(
+  Peripherals(..),
+  ReadResponse,
+  WriteResponse,
+  Bus.read,
+  Bus.write,
+) where
 
 import Clash.Prelude
 
 import Peripherals.Ram(Ram, RamLine, read, RamAddr)
 import Peripherals.Uart(UartAddr, read, write)
-import Machine(Peripherals(..))
+
 import BusTypes(
     BusError(..),
     TransactionSize(..),
     ReadRequest(..),
     BusResponse(..),
     BusVal(..),
-    ReadResponse(..),
-    WriteResponse(..)
   )
 import Types(Addr,
              Byte, HalfWord, FullWord, DoubleWord, QuadWord)
-import Peripherals.Ram(read, bytesInRam)
+import Peripherals.Ram(read, write, bytesInRam)
 import Distribution.Types.UnitId (DefUnitId(unDefUnitId))
 
+data Peripherals = Peripherals
+  {
+      ram  :: Ram
+  }
+  deriving (Generic, Show, Eq, NFDataX)
+
+type ReadResponse = Either BusError BusVal
+type WriteResponse = Either BusError Peripherals
+
+busValToTransactionSize :: BusVal -> TransactionSize
+busValToTransactionSize (BusByte _)       = SizeByte
+busValToTransactionSize (BusHalfWord _)   = SizeHalfWord
+busValToTransactionSize (BusFullWord _)   = SizeFullWord
+busValToTransactionSize (BusDoubleWord _) = SizeDoubleWord
+busValToTransactionSize (BusQuadWord _)   = SizeQuadWord
+
 alignCheck :: Addr -> TransactionSize -> Bool
 alignCheck addr SizeByte       = True
 alignCheck addr SizeHalfWord   = addr `mod` 2 == 0
@@ -50,15 +70,24 @@ read (Request addr size) peripherals
       uartAddr :: UartAddr
       uartAddr = resize uartAddrNoOffset
 
--- write :: BusVal -> Addr -> Peripherals -> IO WriteResponse
--- write val addr peripherals
---   | (addr >= uartStart) && (addr <= uartEnd) =
---       WriteResponse . Result <$> Peripherals.Uart.write val uartAddr
---     where
---       ramAddrNoOffset = addr - ramStart
---       ramAddr :: RamAddr
---       ramAddr = resize ramAddrNoOffset
+write :: BusVal -> Addr -> Peripherals -> IO WriteResponse
+write val addr peripherals
+  | not (alignCheck addr $ busValToTransactionSize val) = return $ Left UnAligned
+  | (addr >= uartStart) && (addr <= uartEnd) =
+      do
+        Peripherals.Uart.write val uartAddr
+        return $ Right peripherals
+  | (addr >= ramStart) && (addr <= ramEnd) =
+      return $ Right $
+        peripherals {
+          ram = Peripherals.Ram.write val ramAddr (ram peripherals)
+          }
+  | otherwise = return $ Left UnMapped
+    where
+      ramAddrNoOffset = addr - ramStart
+      ramAddr :: RamAddr
+      ramAddr = resize ramAddrNoOffset
 
---       uartAddrNoOffset = addr - uartStart
---       uartAddr :: UartAddr
---       uartAddr = resize uartAddrNoOffset
+      uartAddrNoOffset = addr - uartStart
+      uartAddr :: UartAddr
+      uartAddr = resize uartAddrNoOffset