bus architecture re-built I think

hs/Cpu.hs

@@ -0,0 +1,37 @@
+{-# LANGUAGE DataKinds #-}
+{-# LANGUAGE NumericUnderscores #-}
+
+module Cpu(
+  RISCVCPU(..),
+  Endian(..),
+  riscvCPUInit) where
+
+import Clash.Prelude
+import Types(Pc, Mem)
+import RegFiles(GPR, FPR, CSR, gprInit, fprInit, csrInit)
+import Peripherals.Ram(Ram)
+
+data Endian = Big | Little
+  deriving (Generic, Show, Eq, NFDataX)
+
+data PrivilegeLevel
+  = MachineMode
+  | SuperVisorMode
+  | UserMode
+  deriving (Generic, Show, Eq, NFDataX)
+
+data RISCVCPU = RISCVCPU
+  { pc  :: Pc,
+    gpr :: GPR,
+    fpr :: FPR,
+    privilegeLevel :: PrivilegeLevel
+  }
+  deriving (Generic, Show, Eq, NFDataX)
+
+riscvCPUInit :: RISCVCPU
+riscvCPUInit =
+  RISCVCPU
+    0
+    gprInit
+    fprInit
+    MachineMode