Yehowshua/RiscV-Formal
Archived
2
0
Fork 0
Code Issues 8 Pull requests Projects Releases Packages Wiki Activity Actions

bus architecture re-built I think

Browse source
This commit is contained in:
Yehowshua Immanuel 2025-02-26 13:05:02 -05:00
parent c8b192cade
commit 5552ad3d4a
9 changed files with 144 additions and 115 deletions
Download patch file Download diff file Expand all files Collapse all files

1
hs/Fetch.hs
View file

@ -13,6 +13,7 @@ import Clash.Prelude
Bits(shiftR, (.&.)) )
import Types(Mem, Addr, Insn)
import Util(endianSwapWord)
import Bus(ReadResponse, WriteResponse, read)
data FetchResult = Instruction Insn
| Misaligned Addr