bus architecture re-built I think

2025-02-26 13:05:02 -05:00 · 2025-02-26 13:05:02 -05:00 · 5552ad3d4a
commit 5552ad3d4a
parent c8b192cade
9 changed files with 144 additions and 115 deletions
--- a/hs/Peripherals/Uart.hs
+++ b/hs/Peripherals/Uart.hs
@ -17,8 +17,6 @@ import Peripherals.UartCFFI (
 import BusTypes (
    TransactionSize(..),
    BusVal(..),
-    ReadResponse(..),
-    WriteResponse(..)
  )
 import GHC.Generics (URec(UAddr), Generic (from))