bus architecture re-built I think

hs/Simulation.hs

@@ -9,11 +9,11 @@ import qualified Prelude as P
 import Peripherals.Setup(setupPeripherals, InitializedPeripherals(..))
 import Peripherals.Teardown(teardownPeripherals)
 import Clash.Prelude
-import Machine(
-  Machine(..),
+import Bus(Peripherals(..))
+import Cpu(
   RISCVCPU(..),
-  Peripherals(..),
-  machineInit, RISCVCPU (RISCVCPU))
+  RISCVCPU (RISCVCPU),
+  riscvCPUInit)
 import Fetch(fetchInstruction, FetchResult (Instruction, Misaligned))
 import Isa.Decode(decode)
 
@@ -27,6 +27,11 @@ data Simulation
   = Success [Machine]
   | Failure String
   deriving (Show)
+data Machine = Machine
+  { cpu :: RISCVCPU,
+    peripherals :: Peripherals
+  }
+  deriving (Generic, Show, Eq, NFDataX)
 
 -- machine :: Machine
 -- machine = machineInit
@@ -69,7 +74,11 @@ simulation args = do
     InitializationError e -> return $ Failure e
     InitializedPeripherals ram -> do
 
-      let initState = machineInit $ Machine.Peripherals ram
+      let initState =
+            Machine {
+              cpu = riscvCPUInit,
+              peripherals = Bus.Peripherals ram
+              }
       sim <- simulationLoop 15 initState
       teardownPeripherals
       return $ Success sim