Yehowshua/RiscV-Formal
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now fetching from ram correctly as ram is 32 bit word not byte indexed

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Yehowshua Immanuel 2025-03-07 21:41:46 -05:00
parent 3f50fe32f8
commit 63a73d3f71
3 changed files with 9 additions and 1 deletions
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4
hs/Bus.hs
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@ -56,7 +56,7 @@ read :: ReadRequest -> Peripherals -> IO ReadResponse
read (Request addr size) peripherals
| not (alignCheck addr size) = return |> Left UnAligned
| (addr >= ramStart) && (addr <= ramEnd) =
return |> Right |> Peripherals.Ram.read size ramAddr (ram peripherals)
return |> Right |> Peripherals.Ram.read size ramWordAddr (ram peripherals)
| (addr >= uartStart) && (addr <= uartEnd) =
fmap Right (Peripherals.Uart.read size uartAddr)
| otherwise = return |> Left UnMapped
@ -64,6 +64,8 @@ read (Request addr size) peripherals
ramAddrNoOffset = addr - ramStart
ramAddr :: RamAddr
ramAddr = resize ramAddrNoOffset
ramWordAddr :: RamAddr
ramWordAddr = resize |> ramAddrNoOffset `shiftR` 2
uartAddrNoOffset = addr - uartStart
uartAddr :: UartAddr