Yehowshua/RiscV-Formal
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added needed context and getting ready to implement execute

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Yehowshua Immanuel 2025-03-10 22:26:38 -04:00
parent b95b2b962a
commit 69f5cdee6a
7 changed files with 115 additions and 87 deletions
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7
hs/Bus.hs
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@ -15,6 +15,7 @@ import Peripherals.Uart(UartAddr, read, write)
import BusTypes(
BusError(..),
TransactionSize(..),
WriteRequest(..),
ReadRequest(..),
BusVal(..),
)
@ -53,7 +54,7 @@ alignCheck addr SizeQuadWord = addr `mod` 16 == 0
-- reading/writing from/to UART is implemented as reading/writing
-- from/to stdin/stdout, so we need IO.
read :: ReadRequest -> Peripherals -> IO ReadResponse
read (Request addr size) peripherals
read (ReadRequest addr size) peripherals
| not (alignCheck addr size) = return |> Left UnAligned
| (addr >= ramStart) && (addr <= ramEnd) =
return |> Right |> Peripherals.Ram.read size ramWordAddr (ram peripherals)
@ -71,8 +72,8 @@ read (Request addr size) peripherals
uartAddr :: UartAddr
uartAddr = resize uartAddrNoOffset
write :: BusVal -> Addr -> Peripherals -> IO WriteResponse
write val addr peripherals
write :: WriteRequest -> Peripherals -> IO WriteResponse
write (WriteRequest addr val) peripherals
| not (alignCheck addr |> busValToTransactionSize val) = return |> Left UnAligned
| (addr >= uartStart) && (addr <= uartEnd) =
do