Yehowshua/RiscV-Formal
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added needed context and getting ready to implement execute

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Yehowshua Immanuel 2025-03-10 22:26:38 -04:00
parent b95b2b962a
commit 69f5cdee6a
7 changed files with 115 additions and 87 deletions
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14
hs/Exceptions.hs
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@ -18,9 +18,9 @@ data Exception =
| SupervisorExternalInterrupt
| MachineExternalInterrupt
| CounterOverflowInterrupt
| InstructionAddressMisaligned Addr
| InstructionAccessFault Addr
| IllegalInstruction Insn
| InstructionAddressMisaligned
| InstructionAccessFault
| IllegalInstruction {insn :: Insn}
| Breakpoint
| LoadAddressMisaligned
| LoadAccessFault
@ -45,8 +45,8 @@ exceptionCode MachineTimerInterrupt = 7
exceptionCode SupervisorExternalInterrupt = 9
exceptionCode MachineExternalInterrupt = 11
exceptionCode CounterOverflowInterrupt = 13
exceptionCode (InstructionAddressMisaligned _) = 0
exceptionCode (InstructionAccessFault _) = 1
exceptionCode InstructionAddressMisaligned = 0
exceptionCode InstructionAccessFault = 1
exceptionCode (IllegalInstruction _) = 2
exceptionCode Breakpoint = 3
exceptionCode LoadAddressMisaligned = 4
@ -71,8 +71,8 @@ isSynchronousException MachineTimerInterrupt = False
isSynchronousException SupervisorExternalInterrupt = False
isSynchronousException MachineExternalInterrupt = False
isSynchronousException CounterOverflowInterrupt = False
isSynchronousException (InstructionAddressMisaligned _) = True
isSynchronousException (InstructionAccessFault _) = True
isSynchronousException InstructionAddressMisaligned = True
isSynchronousException InstructionAccessFault = True
isSynchronousException (IllegalInstruction _) = True
isSynchronousException Breakpoint = True
isSynchronousException LoadAddressMisaligned = True