added needed context and getting ready to implement execute

hs/Fetch.hs

@@ -20,32 +20,32 @@ import BusTypes(
 import Exceptions(Exception(..))
 import Util((|>))
 
-data FetchResult  = Instruction Insn
-                   | InstructionException Exception
+data FetchResult  = Instruction {insn :: Insn, insnAddr :: Addr}
+                   | InstructionException {exception :: Exception, addr :: Addr}
                    deriving (Generic, Show, Eq, NFDataX)
 
 
 fetchInstruction :: Peripherals -> Addr -> IO FetchResult
 fetchInstruction peripherals addr =
   do
-    readReasponse <-Bus.read (BusTypes.Request addr BusTypes.SizeFullWord) peripherals
+    readReasponse <-Bus.read (BusTypes.ReadRequest addr BusTypes.SizeFullWord) peripherals
     case readReasponse of
       Right (BusFullWord insn) ->
-        pure |> Instruction insn
+        pure |> Instruction insn addr
       Left  UnAligned ->
-        pure |> InstructionException (InstructionAddressMisaligned addr)
+        pure |> InstructionException InstructionAddressMisaligned addr
       Left  UnMapped ->
-        pure |> InstructionException (InstructionAccessFault addr)
+        pure |> InstructionException InstructionAccessFault addr
       Right _ ->
-        pure |> InstructionException (InstructionAccessFault addr)
+        pure |> InstructionException InstructionAccessFault addr
 
 debugInsn :: FetchResult -> String
-debugInsn fetchResult =
-  case fetchResult of
-    Instruction insn ->
-      "Instruction raw binary | "
-        P.++ binaryInsn
-        P.++ " (" P.++ show insn P.++ ")"
-      where
-        binaryInsn = show (bitCoerce insn :: BitVector 32)
-    InstructionException e -> show e
+debugInsn = show
+  -- case fetchResult of
+  --   Instruction insn ->
+  --     "Instruction raw binary | "
+  --       P.++ binaryInsn
+  --       P.++ " (" P.++ show insn P.++ ")"
+  --     where
+  --       binaryInsn = show (bitCoerce insn :: BitVector 32)
+  --   InstructionException e -> show e