Yehowshua/RiscV-Formal
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working on adding read stage

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Yehowshua Immanuel 2025-03-07 12:09:08 -05:00
parent 4cc8c8d430
commit 6b81cd28ee
4 changed files with 24 additions and 10 deletions
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4
rv_formal.cabal
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@ -87,8 +87,11 @@ library
exposed-modules:
Simulation
other-modules:
Fetch,
Decode,
DecodeTypes,
Execute,
Read,
Peripherals.Ram,
Peripherals.Uart,
Peripherals.UartCFFI,
@ -99,7 +102,6 @@ library
BusTypes,
Cpu,
RegFiles,
Fetch,
Exceptions,
Util
c-sources: c/uart_sim_device.c