Yehowshua/RiscV-Formal
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read getting closer to being done

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This commit is contained in:
Yehowshua Immanuel 2025-02-25 19:09:37 -05:00
parent 1f9bd2f015
commit 7265728932
4 changed files with 78 additions and 52 deletions
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6
hs/BusTypes.hs
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@ -11,8 +11,6 @@ module BusTypes(
import Clash.Prelude
import Peripherals.Ram(Ram, RamLine)
import Machine(Peripherals(..))
import Types(Addr,
Byte, HalfWord, FullWord, DoubleWord, QuadWord)
@ -24,7 +22,7 @@ data BusError
data TransactionSize
= SizeByte
| SizeHalfWord
| SizeWord
| SizeFullWord
| SizeDoubleWord
| SizeQuadWord
deriving (Generic, Show, Eq, NFDataX)
@ -40,7 +38,7 @@ data BusResponse a
data BusVal
= BusByte Byte
| BusHalfWord HalfWord
| BusWord FullWord
| BusFullWord FullWord
| BusDoubleWord DoubleWord
| BusQuadWord QuadWord
deriving (Generic, Show, Eq, NFDataX)