more progress on UART read

2025-02-25 23:47:00 -05:00 · 2025-02-25 23:47:00 -05:00 · 8d5cd862ab
commit 8d5cd862ab
parent 7265728932
9 changed files with 77 additions and 31 deletions
--- a/hs/Fetch.hs
+++ b/hs/Fetch.hs
@ -6,6 +6,11 @@ module Fetch(
  FetchResult(..)) where

 import Clash.Prelude
+    ( Eq((==)),
+      KnownNat,
+      Bool(False, True),
+      (!!),
+      Bits(shiftR, (.&.)) )
 import Types(Mem, Addr, Insn)
 import Util(endianSwapWord)