more progress on UART read

hs/Simulation.hs

@@ -8,7 +8,6 @@ module Simulation(Args(..), simulation, Simulation(..)) where
 import qualified Prelude as P
 import Peripherals.Setup(setupPeripherals, InitializedPeripherals(..))
 import Peripherals.Teardown(teardownPeripherals)
-import Text.Printf (printf)
 import Clash.Prelude
 import Machine(
   Machine(..),
@@ -17,12 +16,8 @@ import Machine(
   machineInit, RISCVCPU (RISCVCPU))
 import Fetch(fetchInstruction, FetchResult (Instruction, Misaligned))
 import Isa.Decode(decode)
-import Isa.Forms(Opcode(..))
-import Peripherals.UartCFFI(writeCharToTerminal)
-import Control.Concurrent (threadDelay)
 
 import Debug.Trace
-import Types (Mem, Addr)
 
 data Args = Args {
     firmware :: FilePath
@@ -64,9 +59,6 @@ simulationLoop :: Int -> Machine -> IO [Machine]
 simulationLoop 0 state = return [state]
 simulationLoop n state = do
   let newState = machine' state
-  -- later use this to display writes from machine to its
-  -- uart peripheral
-  -- writeCharToTerminal 'a'
   rest <- simulationLoop (n - 1) newState
   return (state : rest)