Yehowshua/RiscV-Formal
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Yehowshua Immanuel 2025-03-10 17:46:06 -04:00
parent ad751a5039
commit b95b2b962a
4 changed files with 82 additions and 39 deletions
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5
hs/Simulation.hs
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@ -15,6 +15,7 @@ import Peripherals.Setup(setupPeripherals, InitializedPeripherals(..))
import Peripherals.Teardown(teardownPeripherals)
import Clash.Prelude
import Bus(Peripherals(..))
import Read(read)
import Cpu(
RISCVCPU(..),
riscvCPUInit)
@ -44,8 +45,8 @@ simulationLoop n machine = do
let machinePeripherals = peripherals machine
currPc = pc |> cpu machine
fetchResult <- fetchInstruction machinePeripherals currPc
let decodeResult = decode fetchResult
putStrLn |> show decodeResult P.++ debugInsn fetchResult
let decodeResult = Read.read (decode fetchResult) (cpu machine)
putStrLn |> show decodeResult -- P.++ debugInsn fetchResult
let pc' = currPc + 4
cpu' = (cpu machine) { pc = pc' }
machine' = machine { cpu = cpu' }