save progress before switching to new bus architecture

2025-03-04 08:12:59 -05:00 · 2025-03-04 08:12:59 -05:00 · d7d698a28c
commit d7d698a28c
parent 88ec010f98
4 changed files with 80 additions and 56 deletions
--- a/rv_formal.cabal
+++ b/rv_formal.cabal
@ -100,8 +100,7 @@ library
    Cpu,
    RegFiles,
    Fetch,
-    Exceptions,
-    Util
+    Exceptions
  c-sources: c/uart_sim_device.c
  include-dirs: c
  default-language: Haskell2010