getting closer...

hs/Machine.hs

@@ -4,12 +4,14 @@
 module Machine(
   Machine(..),
   RISCVCPU(..),
+  Peripherals(..),
   Endian(..),
   machineInit) where
 
 import Clash.Prelude
 import Types(Pc, Mem)
 import RegFiles(GPR, FPR, CSR, gprInit, fprInit, csrInit)
+import Peripherals.Ram(Ram)
 
 data Endian = Big | Little
   deriving (Generic, Show, Eq, NFDataX)
@@ -20,6 +22,12 @@ data PrivilegeLevel
   | UserMode
   deriving (Generic, Show, Eq, NFDataX)
 
+data Peripherals = Peripherals
+  {
+      ram :: Ram
+  }
+  deriving (Generic, Show, Eq, NFDataX)
+
 data RISCVCPU = RISCVCPU
   { pc  :: Pc,
     gpr :: GPR,
@@ -30,7 +38,7 @@ data RISCVCPU = RISCVCPU
 
 data Machine = Machine
   { cpu :: RISCVCPU,
-    mem :: Mem 14
+    peripherals :: Peripherals
   }
   deriving (Generic, Show, Eq, NFDataX)
 
@@ -42,11 +50,11 @@ riscvCPUInit =
     fprInit
     MachineMode
 
-machineInit :: Machine
-machineInit =
+machineInit :: Peripherals -> Machine
+machineInit peripherals =
   Machine
     riscvCPUInit
-    memInit
+    peripherals
 
 memInit :: Vec 14 (Unsigned 32)
 memInit =