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RiscV-Formal/hs/Fetch.hs
2025-03-04 23:43:35 -05:00

38 lines
1.1 KiB
Haskell

{-# LANGUAGE DataKinds #-}
{-# LANGUAGE NumericUnderscores #-}
module Fetch(
fetchInstruction,
FetchResult(..),
) where
import Clash.Prelude
import Types(Mem, Addr, Insn)
import Bus(ReadResponse, WriteResponse, read)
import Bus(Peripherals(..))
import BusTypes(
ReadRequest(..),
TransactionSize(..),
BusVal(..),
BusError(..))
import Exceptions(Exception(..), exceptionCode, isSynchronousException)
import GHC.IO (IO)
import GHC.Base (Applicative(pure))
data FetchResult = Instruction Insn
| InstructionException Exception
fetchInstruction :: Peripherals -> Addr -> IO FetchResult
fetchInstruction peripherals addr =
do
readReasponse <-Bus.read (BusTypes.Request addr BusTypes.SizeFullWord) peripherals
case readReasponse of
Right (BusFullWord insn) ->
pure $ Instruction insn
Left UnAligned ->
pure $ InstructionException InstructionAddressMisaligned
Left UnMapped ->
pure $ InstructionException InstructionAccessFault
Right _ ->
pure $ InstructionException InstructionAccessFault