Yehowshua
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Yehowshua opened issue ReferenceProjects/riscv-bluespec-classic#21 2025-04-21 11:30:31 +00:00
Explicitly Enumerate Server Semantics
Yehowshua commented on issue ReferenceProjects/riscv-bluespec-classic#20 2025-04-21 00:30:07 +00:00
Explicitly qualify more identifiers in Bus.bs

Need to ask on mailing list how to do this... compiler doesn't like my first attempt:

[nix-shell:~/git/riscv-bluespec-classic]$ bsv2bsc bsv/CBindings.bsv 
package CBindings(initTermina…
Yehowshua opened issue ReferenceProjects/riscv-bluespec-classic#20 2025-04-20 23:26:48 +00:00
Explicitly qualify more identifiers in Bus.bs
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-20 22:06:21 +00:00
842c19d441 make server map, normalize uart interfaces
Yehowshua opened issue ReferenceProjects/riscv-bluespec-classic#19 2025-04-20 21:57:50 +00:00
Convert BDPI from bsv to bs
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-20 19:22:19 +00:00
7290af88fb scaffolding for new uart interface in place
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-20 02:04:44 +00:00
89664a01f6 reduce noise in tag engine unit test as well as make results apparent
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-20 01:51:39 +00:00
2d9bc945c5 improve simulation egornomics a bit
Yehowshua merged pull request ReferenceProjects/riscv-bluespec-classic#18 2025-04-20 00:48:04 +00:00
flake: Add missing input
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-20 00:48:04 +00:00
f2a464b090 Merge pull request 'flake: Add missing input' (#18) from Artturin/riscv-bluespec-classic:fix-compat into main
9d897fccdc flake: Add missing input
Compare 2 commits »
Yehowshua commented on issue ReferenceProjects/riscv-bluespec-classic#8 2025-04-19 01:59:24 +00:00
Add Unit Tests

exit code should be non-zero when assert fails

Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-18 23:42:06 +00:00
44324eb803 need to start re-thinking structure of uart etc
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-18 19:35:19 +00:00
d03cceb283 Merge pull request 'Add flake' (#7) from Artturin/riscv-bluespec-classic:addflake into main
7bc43946a9 Add compat files for non flakes users
b89090f3ce flake.lock: Update
c02e7b0de6 flake: Install the same file that fpga-starter-project-uart installed
7471c0188a Make make fpga work
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Yehowshua merged pull request ReferenceProjects/riscv-bluespec-classic#7 2025-04-18 19:35:19 +00:00
Add flake
Yehowshua opened issue ReferenceProjects/riscv-bluespec-classic#17 2025-04-18 02:50:43 +00:00
Verify Behaviors of Interest for Builtin Bluespec Arbiter.bsv Library
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-04-18 02:48:23 +00:00
d552934b95 Fixed grant bug
Yehowshua closed issue ReferenceProjects/riscv-bluespec-classic#3 2025-04-18 01:49:57 +00:00
Tag Engine Notes
Yehowshua commented on issue ReferenceProjects/riscv-bluespec-classic#3 2025-04-18 01:49:56 +00:00
Tag Engine Notes

Ended up implementing a FIFO based free list. I'd say this is done at present and that this issue can be close.

Yehowshua commented on issue ReferenceProjects/riscv-bluespec-classic#5 2025-04-18 01:48:31 +00:00
Need to Support Retiring and Reuquesting Tag externally in the same rule

I believe I've confirmed that this is presently possible.

Yehowshua closed issue ReferenceProjects/riscv-bluespec-classic#5 2025-04-18 01:48:31 +00:00
Need to Support Retiring and Reuquesting Tag externally in the same rule