Yehowshua
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Yehowshua opened issue ReferenceProjects/riscv-bluespec-classic#1 2025-03-14 16:31:04 +00:00
Add Proper Nix Flake
Yehowshua pushed to main at ReferenceProjects/riscv-bluespec-classic 2025-03-14 16:30:47 +00:00
66464daf0c Update README.md
Yehowshua renamed repository from main to ReferenceProjects/riscv-bluespec-classic 2025-03-14 16:29:42 +00:00
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-14 15:55:42 +00:00
966fd30fa2 Merge pull request 'Add flake' (#4) from Artturin/RiscV-Formal:addnix into main
8037eeba19 flake.nix: Remove cross glibc
0960ceb53a rv_tests/hello_world: Rename PREFIX var to CROSS_PREFIX and make it configurable
ac8a2ea238 flake.nix: Comments
56a80fe749 Riscv config
Compare 11 commits »
Yehowshua merged pull request Yehowshua/RiscV-Formal#4 2025-03-14 15:55:41 +00:00
Add flake
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-13 20:26:08 +00:00
a76d6e24ec correct behavior of R type in execute
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-13 18:31:43 +00:00
4428f7f196 fixed execution of R type instructions
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-11 03:00:28 +00:00
7066df0936 Grok mostly wrote execute - will test later...
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-11 02:26:42 +00:00
69f5cdee6a added needed context and getting ready to implement execute
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-10 21:46:12 +00:00
b95b2b962a read seemingly complete
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-10 21:23:43 +00:00
ad751a5039 read is getting there...
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-08 03:04:45 +00:00
171fcece98 reduce debug in sim and add PREFIX to makefile
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-08 02:41:50 +00:00
63a73d3f71 now fetching from ram correctly as ram is 32 bit word not byte indexed
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-08 01:31:45 +00:00
3f50fe32f8 still compiling after refactoring field types
Yehowshua commented on issue Yehowshua/RiscV-Formal#12 2025-03-08 00:12:07 +00:00
Make CSR Content Addressable

The closest we can get to "CSR does not exist" is perhaps "Illegal Instruction Exception"

Yehowshua opened issue Yehowshua/RiscV-Formal#12 2025-03-08 00:10:54 +00:00
Make CSR Content Addressable
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-07 23:41:59 +00:00
73d5e1204c stopping point before re-factoring decoder types
6b81cd28ee working on adding read stage
Compare 2 commits »
Yehowshua closed issue Yehowshua/RiscV-Formal#2 2025-03-06 13:49:56 +00:00
Generalize Memory Access
Yehowshua commented on issue Yehowshua/RiscV-Formal#2 2025-03-06 13:49:56 +00:00
Generalize Memory Access

done

Yehowshua closed issue Yehowshua/RiscV-Formal#11 2025-03-06 13:49:22 +00:00
Replace $ with custom |> operator