Yehowshua

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• https://yehowshuaimmanuel.com
• Joined on 2024-12-29

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Yehowshua commented on issue Yehowshua/RiscV-Formal#11 2025-03-06 13:49:22 +00:00

Replace $ with custom |> operator

Resolved as of 4cc8c8d430

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-06 13:44:43 +00:00

4cc8c8d430 Forgot to replace $ operator in Uart.hs

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-06 13:41:30 +00:00

0792bf3c7d Replacing $ operator with more readable |> operator

Yehowshua opened issue Yehowshua/RiscV-Formal#11 2025-03-05 14:07:02 +00:00

Replace $ with custom `

Yehowshua opened issue Yehowshua/RiscV-Formal#10 2025-03-05 14:06:09 +00:00

Probably more useful to have Add instead of Insn in IllegalInstruction Exception variant

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 14:05:19 +00:00

2b1c486c17 created Decode result

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 05:11:02 +00:00

a6c435791a improve instructions to simulate in README

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 05:09:11 +00:00

7f7ba49ee1 prune more warnings and re-org Decode files a bit

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:54:37 +00:00

67b44dedc0 clean up warnings a bit

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:43:48 +00:00

30650b870c replace/update relevant fetch types and functions

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:37:43 +00:00

eb79210863 now using bus and new FetchResult type

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:05:55 +00:00

4729d79b23 refactoring towards types that can handle exceptions between stages

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-04 13:13:04 +00:00

d7d698a28c save progress before switching to new bus architecture

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-03 04:12:06 +00:00

88ec010f98 initial support for exceptions

Yehowshua opened issue Yehowshua/RiscV-Formal#9 2025-03-02 08:02:30 +00:00

Add Mtime peripheral

Yehowshua opened issue Yehowshua/RiscV-Formal#8 2025-03-02 07:16:41 +00:00

Implement Exception Handling in Exceptions.hs

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 18:05:06 +00:00

5552ad3d4a bus architecture re-built I think

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 07:24:27 +00:00

c8b192cade prep for notable re-org

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 06:51:37 +00:00

024115e389 Uart now has correct write implementation presumably

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 04:47:04 +00:00

8d5cd862ab more progress on UART read